Known 3-transistor (3-T) buried-gated photodiode devices, often referred to as 3-T pinned photodiode devices, are normally not suitable for use in windowed arrays due to the fact that the electrical charge on the floating diffusion (FD) node of the photodiode device can vary, i.e., float. This feature of the 3-T pinned photodiode device makes it unsuitable for use as a pixel in a windowed array because the floating nature of the FD node can result in a non-addressed pixel inadvertently driving the pixel output line connected to the pixel.
FIG. 1 illustrates a schematic diagram of a known 3-T buried-gated photodiode device 2, which is commonly referred to as a pixel. The pixel 2 includes a photodiode 3, a transfer transistor 4, a reset transistor 5, and a source follower (SF) transistor 6. The source of the reset transistor 5 is tied to the FD node 7 of the photodiode device 2. The drain of the reset transistor 5 is tied to a line called pixel VDD (PVDD). The PVDD line 13 is tied to a pixel output line 14, which includes a switch 8, labeled FDLOW bar, and to a switch 9, labeled FDLOW. FDLOW bar is FDLOW inverted. The source of the SF transistor 6 is tied to an output terminal 12, which is tied to a current source 11. The current source 11 is tied to ground. The drain of the SF transistor 6 is tied to the PVDD line 13. The pixel 2 operates as follows. When the pixel 2 is in an exposure reset period, the switch FDLOW bar 8 is closed (i.e., asserted), which conductively connects line PVDD to VDD. The reset signal (RS) of the reset transistor 5 is toggled from low to high to low, which activates the reset transistor 5 and causes the FD node 7 to charge to VDD. The transfer signal, TX, received at the gate of the transfer transistor 4 is then toggled from low to high to low, which causes the photodiode 3 to be set to the fully depleted photodiode voltage. An integration period then occurs during which photons strike the photodiode 3 causing electrical charge to accumulate on the photodiode 3.
At the end of the integration period, an FD reset period occurs. While the FDLOW bar switch 8 remains closed, the reset signal RS is again toggled from low to high to low, which activates the reset transistor 5 and causes the FD node 7 to charge to VDD. Just before the end of the settle period, the voltage on output line 12 is read by a sample-and-hold (S/H) circuit (not shown). This sampled value is called the reset read value.
At the end of the first settle period (after the reset read value has been sampled) a transfer period occurs during which the TX signal is again toggled from low to high to low. This causes the charge on the photodiode 3 to be transferred from the photodiode 3 to the FD node 7. A settle period then occurs to allow the output line 12 to settle to its steady state value. Just before the end of the settle period, the value on the output line 12 is sampled by the S/H circuit. This sampled value is called the video read value.
At the end of the second settle period (after the video read value has been sampled), the FDLOW switch 9 is closed (FDLOW bar switch 8 is opened), which causes the PVDD line to be pulled down nearly to ground. The reset signal RS is asserted, which activates the reset transistor 5 and causes the FD node 7 to be pulled down to ground. Just before the FDLOW switch 9 is opened, the reset signal RS is deasserted, which deactivates the reset transistor 5, thereby causing the low value to be stored on the FD node 7. The FDLOW switch 9 is then opened (FDLOW bar switch 8 is closed), which pulls the PVDD line up to VDD.
The low voltage (ground or nearly ground) stored on the FD node 7 is intended to remain low whenever the pixel 2 is not being addressed. However, because the voltage stored on the FD node 9 tends to float, it is possible for that voltage to increase to a level that is sufficient to turn on the SF transistor 6. This would produce a voltage on output line 12, which, in a windowed array, is part of the pixel output line. If this happens at a time when another pixel in the same column is being addressed, the sampled value of that pixel will be corrupted. For this reason, 3-T pinned photodiode devices normally are not used in windowed arrays.
Pixels in windowed arrays typically are 4-T buried-gated (or pinned) photodiode devices. These pixels have additional transistors that ensure that a pixel is not driving the pixel output line unless the pixel is being addressed. However, the additional transistors and the corresponding additional control lines consume additional area on the IC, which leaves less area for the photodiode. It would be desirable to be able to use a 3-T burried-gated photodiode devices in a windowed array so that less area is needed for transistors and control lines, leaving more area for the photodiode.